Resume

Career Interest

Digital signal processor semiconductor IP core architecture and design for ASICs or FPGAs. Freedom to publish.

Employment History

• Assisted the development of industry-leading video and image digital signal processing cores through research.

• Advised customers and prospective customers on system level design decisions around the ARC Video subsystem including hardware bus protocol, memory controller bandwidth and features, audio and broadcast time stamp sync, and software control API interfacing.
• Travelled to sales and support meetings in Tokyo, Osaka, Nara, Iwaki, and Fukuoka Japan, Seoul and Suwon South Korea, Taipei and Hsinchu Taiwan, and Shanghai and Beijing China.
• Advised marketing department on video processor IP core product requirements for mobile entertainment, home theater, camcorder, video conferencing, and automotive safety critical video systems.
• Publicized the company's expertise in video subsystem IP cores through participation in the SMPTE and MPEGIF industry standard bodies, giving presentations at conferences, and publication of articles.
• Conceived of inventions and pursued patents.

• Completed the Ultra Data video processor design by extending the DSP core ISA with new and enhanced instructions, a local data memory and fifos, and an interprocessor communications infrastructure.
• Optimized video processor microarchitecture for synthesis at 400 MHz for a UMC fab 0.13 micron process technology.
• Assisted in the prosecution of patents on my work.

• Negotiated and closed an acquisition of the company's assets by Micronas, yielding a better than break-even return on investment for Ultra Data shareholders.
• Achieved the world's first programmable processor architecture with the performance required to decode AVC (H.264), VC-1 (WMV9), MPEG-2, MPEG-4, and other widely used video standards for HDTV at 1920x1080 resolution and 30 frames per second.
• Architected and implemented in HDL a multiprocessor video decoder system based on 2 RISC and 3 DSP cores with 5 single-cycle throughput dual-port data RAMs, and an intelligent DMA controller connected through a non-blocking crossbar switch fabric.
• Architected and implemented in HDL a VLIW 64-bit 4/8-way SIMD DSP core, optimized for video processing, with a pipelined multiplier, a specialized ALU, a 5-port register file, and a specialized load/store interface.
• Wrote papers, presented at conferences, chaired panels, gave lectures, evangelized video processor technology, developed marketing collateral, and built and maintained a respected corporate brand identity.
• Initiated sales with top-ten semiconductor and top-five consumer product vendors and managed deals through due diligence.
• Designed and verified hardware for 25 CorExtend instructions to enhance the performance of MIPS Technologies processor cores on G.729 VoIP applications by SIMD methods.

• Designed synthesizable, 500 MHz, high-performance, Mips32 multiply-accumulator/divider (MAC) for .13μm process technologies and led the design verification.
• Designed synthesizable high bandwidth crossbar for cache coherent multiprocessors, from spec through RTL to timing closure with special attention to routing requirements.
• Designed semi- and full-custom critical path elements, modeled and simulated with SPICE, for use in structured custom circuit design.
• Designed 32-bit configurable 3 to 8 port register file for single-issue and superscalar MIPS processor cores to support synthesized and structural latch, flop, and RAM based implementation in ASICs and FPGAs.
• Designed, tested, documented, published, and supported PLD-based hardware/software development board, including Verilog simulation model, and synthesizable system peripherals.
• Enhanced the testbed and created functional verification tests for 32-bit MIPS processors.

• Developed manufacturing tests for digital and mixed-signal tester channel cards for disk drive chips.

• Automated manufacturing test and board-level debug of PCI screener and film file processor boards.
• Designed general-purpose PC peripheral hardware to perform testing.

Consulting Projects

• Advised president on video technology
• Worked with manufacturers and distributors to specify the LalaDock hardware BOM

• Developed a specification for an H.264 I-frame decoder IP core and assisted in sales support.

• Wrote an opinion and testified as an expert witness in a binding arbitration case.

• Developed an IP core design specification.

Community Projects

• Documented and routinely updated listings of the market focus, products, customers, vendors, and partners of hundreds of semiconductor IP core, chip, board, software, and system companies in the digital video business.
• Published a web-based tutorial on the principles of digital video complete with pictures, diagrams, and easy to understand examples.
• Maintained contact with technology implementers and senior managers throughout the digital video business by connecting people with opportunities, answering questions, and lending insight on markets and technologies.

• Contribute research in a broad range of fields under the user name Panscient.

Education

• Architected, designed, and prototyped Methos 16-bit RISC processor core.
• Three years instructing a freshman class on compact disc technology.

Honors & Credited Publications

• IEEE Journal of VLSI Signal Processing Systems article on Architecture Considerations for Multi-Format Programmable Video Processors.
• Portable Design magazine article on Minimizing Power Consumption in a Mobile Video Subsystem.
• DSP DesignLine article Memory bandwidth metrics for video processing.
• GSPx 2006 panelist on Integrating IP in Multicore DSP/Processor SoCs.
• GSPx 2006 paper System Design Tricks for Low-Power Video Processing.
• 2006 Picture Coding Symposium Beijing invited paper Architecture Considerations for Multi-Format Programmable Video Processors.
• 2005 International Engineering Consortium DesignVision Award nominee for Ultra Data UD3000 video processor.
• Data movement within a processor U.S. patent application number 20060206695
• Processor system that allows for simultaneous access by multiple requestors to a target with multiple ports U.S. patent application number 20060282588
• DesignCon 2005 program committee member and chair of panel The Trade-Offs of Software Programmability in Video Processors.
• GSPx 2004 paper What Choices Make a Killer Video Processor Architecture.
• TechOnLine article Processor Architecture for High Performance Video Decode.
• Embedded Processor Forum 2004 paper The Ultra Data UD3000: A Next Generation Video Processor Core.
• Guest lecturer on digital video technology at Cornell University.
• DesignCon 2004 paper Improving Application Performance with Instruction Set Architecture Extensions to Embedded Processors.
• Microprocessor Forum 2001 paper LX5380 RISC-DSP for New Internet Applications.
• Integrated Communication Design Magazine article Considerations for the Design of a Reusable SOC Hardware/Software Development Board.
• DesignCon 2000 paper Verification of Lexra Processor Cores.
• Microprocessor Forum 1999 paper LX5280 High-Performance RISC-DSP for IP Licensing.
• Westinghouse 1994 semifinalist project Identifying Bacteria by Their Reflectance Spectra.

Skills

Windows, Linux, Unix, and Solaris EDA tools including VCS, Verilog NC/XL, ModelSim, Synopsys Design Compiler, Prime Time, Synplicity Synplify ASIC, HSpice, Synplicity Synplify, Altera Quartus, Xilinx ISE, Verilint, Blue Pearl Indigo. Also Perl, Bash shell, C, and assembly language programming. As well as PC and workstation administration and networking, including Hummingbird Exceed, VNC, and Microsoft Word, Excel, PowerPoint, Adobe Frame Maker, Acrobat, Photoshop, and Quark Xpress document editing and HTML, XML, XSL, PHP, and CSS web design.